IBM/Lenovo compatible

RAM Modules

This module consists of chips that are divided into individual sections. Each section consists of a matrix where the columns are formed by capacitors and the rows by transistors. Capacitors are cells that store an electrical charge. If they are charged, they represent the value 1; the opposite means 0. The catch is that capacitors cannot effectively retain charge and gradually discharge, therefore the charge must be constantly renewed. This renewal takes place every few tens of milliseconds and is called memory refresh.

When reading data from a RAM module, the memory controller plays a major role. Thanks to it, RAM can provide speeds several times higher compared to disks. The controller uses the cache principle, where it writes data addresses across the individual matrices and is able to activate the Wordline (row controller) and Bitline (column controller). When the Wordline is activated, all transistors of the given row are opened. Thanks to this, the capacitors under these open transistors are connected to the Bitline. Each column controller then reads the voltage of each capacitor from the “open” row and based on that decides whether the capacitor represents the value 1 or 0. And since each column reads one value, one row of binary code is created, which is sent out of the module as output data. This process consumes all charge, and therefore the columns amplify the read charge and recharge the capacitors.

Data writing takes place similarly to reading. The transistors are opened again, thereby connecting the capacitors with the Bitline. This time, the Bitline columns do not serve as an imaginary voltage reader but as a generator. Therefore, for each capacitor that should carry the value 1, the column generates high voltage with which it charges the capacitors. After the writing is completed, RAM is natively able to refresh the charge.

Rank

Rank can be imagined as a description of the bus through which the processor communicates with memory. The bus has a width of 64 bits. These total 64 bits for communication are divided among the individual chips. Therefore, if we see a rank value of 1Rx8, it means we have one set of chips that together provide 64 bits for communication (each of the eight chips has an 8-bit communication bus). Today, however, we much more frequently encounter the term dual-rank. This means that the module has two sets of chips, each of which can individually utilize the 64-bit bus (the sets are typically on opposite sides of the module). Each time the processor communicates with memory, a set needs time to refresh the charge. Instead of the processor waiting for one set, it can immediately communicate with the other set, thereby practically multiplying the speed of data flow. When selecting suitable RAM, rank must be respected across all modules you purchase. Combining different memory ranks may cause instability or complete system failure.

Frequency

Frequency specified in MHz indicates how many operations the memory module performs per second. As a rule, the higher the frequency of RAM, the faster the memory processes instructions.

With DDR4 memory, we commonly encounter frequencies from 2,133 to 4,600 MHz; with the latest DDR5 technology from 4,800 to 6,400 MHz. In recent years, MT/s has become a popular unit. It indicates how many data transfers per second the module can handle.

DDR Generation

DDR (Double Data Rate) memory is a multi-generation standard of RAM. It is the most popular type on the market.

Nowadays, despite their limited availability and rising prices, both older DDR4 memory and DDR5 are popular. With DDR5 memory, we also encounter the new MRDIMM (Multiplexed Rank Dual In-Line Memory Module) standard. It is not intended as a replacement for DDR5 memory, but rather as a “power-up” of this technology. It addresses one of the main bottlenecks of modern servers — memory bandwidth — which is approximately 50% higher with MRDIMM.

For logical reasons, DDR modules are not backward compatible, and any upgrade must be accompanied by purchasing a new motherboard.

ECC

This is Error-Correcting Code technology, which allows RAM to correct data. During operation, it is common for bit errors to occur, and ECC is capable of correcting these errors and restoring the record. ECC memory works by appending several control bits to stored data based on mathematical processes. If a single-bit error occurs, RAM can recalculate the mathematical relationship between data and ECC bits and correct the error. For multi-bit problems, this works only with some modules; however, even modules without this capability can detect multi-bit errors and thus prevent data corruption.

CAS Latency

CAS Latency (Column Address Strobe Latency), also referred to as timing, determines how many cycles pass between a read command and the first returned data. This latency significantly affects memory speed and strongly depends on frequency in DDR memory. Therefore, it is defined in clock cycles rather than fixed time. Modules with different timings are not compatible within the same system.